1. Field of the Invention
Embodiments of the invention relate to semiconductor memory devices. More particularly, embodiments of the invention relate to NAND flash memory devices and programming methods having improved speed during a multi-level cell programming operation.
A claim of priority is made to Korean Patent Application 10-2005-0088848 filed on Sep. 23, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Various semiconductor memory devices have been developed to store and subsequently provide data. Semiconductor memory devices may be classified into random access memory (RAM) and read only memory (ROM). The RAM is a volatile memory device in which stored data disappears when power is turned off. The ROM is nonvolatile memory device in which stored data is retained even if power is turned off. The RAM includes dynamic RAM (DRAM), static RAM (SRAM), etc. The ROM includes programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), flash memory, etc. Flash memory devices may be further classified as NAND flash memory devices and NOR flash memory devices.
NAND flash memory devices store multi-bit data on a single memory cell. A memory cell adapted to store multi-bit data is referred to as a multi-level cell (MLC). MLCs have multiple programmable states. For example, an MLC storing 2-bit data will have four (4) programming states that vary by threshold voltage and correspond one for one to data values ‘11’, ‘10’, ‘00’ and ‘01’. Within this context, the programming states and the corresponding data values include a least significant bit (LSB) of data and a most significant bit (MSB) of data.
Conventional NAND flash memory devices often use an incremental step pulse program (ISPP) method that is well adapted for use with a range of threshold voltages defining multiple programming states for an MLC. In the ISPP method, a final program voltage is not applied to a selected word line all at once during a programming operation, but is applied to the selected word line incrementally according to a defined programming routine.
A method for programming multi-bit data on an MLC is referred to as an MLC programming method. A 2-bit MLC programming method, for example, may be divided into an LSB programming operation adapted to program the LSB data, and an MSB programming operation adapted to program the MSB data. During the LSB programming operation, a corresponding LSB program voltage is applied to a selected word line, and a corresponding MSB program voltage is applied to a selected word line during the MSB programming operation.
A NAND flash memory device that performs an MLC programming operation using the conventional ISPP approach, typically uses an identical start voltage during the LSB programming operation and the MSB programming operation. That is, the conventional NAND flash memory device used an LSB start voltage and an MSB start voltage having similar levels. The LSB start voltage is a program voltage initially applied during an LSB programming operation, and the MSB start voltage is a program voltage initially applied during an MSB programming operation.
When the LSB programming operation is performed, the memory cell has a ‘11’ state or a ‘10’ state. AN MLC in a ‘10’ state has a threshold voltage higher than that of an MLC in a ‘11’ state. Thus, when an MSB programming operation is performed, an MLC cell in a ‘11’ state will transition to a ‘01’ state, while an MLC in a ‘10’ state will transition to a ‘00’ state.
Since the threshold voltage applied to an MLC increases through the LSB programming operation of the conventional programming methods, the fact that similar LSB and MSB start voltages are used becomes a significant consideration in any attempt to improve programming operation speed.